Open Source
Towards Building a Trusted Execution Environment on RISC-V Microcontrollers
In this article we share our experience of developing a secure system using RISC-V Micro-Controller Unit (MCU). If this topic resonates, we encourage you to join our mTower project to explore the potential of RISC-V security.
RISC-V Open Architecture
RISC-V has rapidly gained popularity among the architectures used for MCU. Its open architecture with a customizable instruction set (ISA) allows developers to tailor processors to specific needs (including security), to reduce the costs and to accelerate innovation.
RISC-V is a lucrative choice because of the following features:
Importance of Trusted Execution Environment for RISC-V Microcontrollers
With the development of IoT technologies, security has become one of the key issues. IoT devices collect, process and transmit large volumes of confidential data, making it essential to ensure secure execution of security-critical operations. A TEE creates an isolated environment within the processor, guaranteeing that security-sensitive functions, such as Trusted Identity, Trusted Boot, Trusted Update, Trusted Firmware, and Trusted Operation, have no risk of compromise (Fig.1).
Figure 1. Security aspects for embedded system
The open and modular architecture of RISC-V provides developers with the flexibility to integrate TEE and explore new approaches to create secure environments for various IoT systems. A distinctive feature of RISC-V-based MCUs is that their development can be done faster comparing to more complex CPUs. This is due to the relative simplicity and accessibility of microcontrollers, both in manufacturing and usage, making them ideal for implementing new features and quickly adapting to new security standards.
Hardware Features for Building TEE Based on RISC-V
Privilege Levels
Privileges management is a fundamental element of security for the Trusted Execution Environment (TEE) built in MCUs. RISC-V architecture allows multiple privilege levels, enabling effective separation of trusted and untrusted processes.
RISC-V supports several execution modes, including Machine mode (M-mode/M), Supervisor mode (S-mode/S), and User mode (U-mode/U)[4][5].
Combinations of modes:
MCUs with both Machine mode and User mode already allow for certain aspects of privilege management, as they can restrict untrusted programs' access to resources. This type of MCU is more prevalent in the industry. MCUs/CPUs that support three modes - Machine mode, User mode, and Supervisor mode - can implement more complex privilege management systems. The presence of Supervisor mode allows for a higher level of control over resources and access, which is critical for security within TEE.
In mTower project, presented below, we used MCUs with only M-mode and U-mode, since they are more widespread and support the required basic privilege management system.
Access Control Using Physical Memory Protection (PMP)
In RISC-V MCUs, the PMP mechanism plays a crucial role in enhancing security and managing access to memory. PMP allows the implementation of access control policies for physical memory addresses, enabling developers to set rules for memory regions[4][5].
Key Aspects of PMP:
o Access Type: whether access is allowed for reading, writing, or executing
o Access Mode: privilege level for the region (e.g., user or supervisor)
Majority of RISC-V MCUs lack support of Input/Output Physical Memory Protection (IOPMP). This can be a limitation for implementing comprehensive security systems, since, without IOPMP, access to peripheral devices cannot be controlled in the same way as memory access.
Other Security Enhancement Mechanisms
In addition to access control, RISC-V-based MCUs can employ a number of other mechanisms to enhance security. Crypto accelerators, for example, are hardware components designed to perform encryption and decryption operations with high efficiency, providing significant speed advantages over software implementations. Many of these accelerators support essential cryptographic algorithms, making them critical for ensuring data confidentiality and integrity.
Furthermore, True Random Number Generators (TRNGs) are utilized to enhance security by providing high-quality random numbers essential for cryptographic operations. TRNGs ensure reliability in key generation, which is vital for data protection.
Thus, the RISC-V architecture offers a platform for implementing security measures through effective privilege management and memory protection mechanisms. The combination of multiple privilege levels and the PMP system enables the reliable separation of trusted and untrusted processes, which is critically important for creating a TEE. By utilizing these mechanisms in mTower project, we have made progress in establishing a secure system. Let's delve deeper into the technical details.
Implementation overview
The mTower project is an experimental industry standard-compliant implementation TEE based on ARM TrustZone for Cortex-M23/33/35p/55 MCUs. It has been expanded to support MCUs based on the RISC-V architecture. From the very beginning, mTower has been designed to have a tiny RAM footprint and to avoid the use of time-consuming operations. The source code of mTower is available at GitHub[6].
The mTower project allows for exploring and implementing protection mechanisms for creating TEE. After examining existing approaches to building secure systems, we were drawn to the method discussed at the RISC-V Summit[11] and used the Si-Five open source code[7].
The initial requirements for implementing TEE included support for M-mode and U-mode in the MCUs, as well as the presence of the PMP memory protection mechanism. For the base operating system for the MCU, we chose FreeRTOS[10], which provides a stable platform for managing trusted and untrusted processes and allows for the efficient utilization of available hardware resources to protect data.
Extension of FreeRTOS
In FreeRTOS, the code can run in both modes: privileged (M) mode (kernel, interrupt handlers, system tasks) and unprivileged (U) mode (user tasks). This allows for the effective separation of security-critical operations from general tasks. The privileged mode provides access to all hardware resources, including memory management and peripheral devices, while unprivileged tasks have restricted access, preventing the possibility of system compromise through uncontrolled access to resources (Fig 2).
Figure 2. Privilege and Non-privileged calls
To restrict access to memory between user tasks on microcontrollers based on the RISC-V architecture, the PMP mechanism is used. PMP allows for configuring access rules for different regions of physical memory depending on the execution mode, which helps to protect critical data and to isolate processes from each other.
This mechanism serves as the foundation for creating more secure environments where each user task has its clearly defined memory access boundaries. In case of direct access to a memory area or resource that is restricted, an exception will be raised.
Due to the limitation on the number of memory regions that can be controlled by the PMP, a mechanism for PMP controller dynamic configuration has been added to the FreeRTOS. It triggers at every task context switch (Fig. 3). This means that with each transition between tasks, the PMP configuration is updated to reflect the new memory access boundaries for the current task. This approach allows to use hardware resources effectively and provides reliable memory access distribution even in systems with limited number of PMP registers.
Figure 3. Processing PMP configuration
The mTower project can run tasks in both privileged and unprivileged modes, which is fundamental feature to manage system resource access securely. The privileged mode grants full access to hardware resources, while unprivileged tasks are restricted, thereby reducing the risk of compromising the system through unauthorized resource access.
Additionally, the mTower dynamically configures the PMP mechanism during each task switch. This allows the definition of memory regions that tasks can access, ensuring process isolation and preventing unauthorized access. Any attempt to violate access rules results in an exception, further strengthening memory protection.
The following demo scenarios were prototyped with mTower:
These scenarios illustrate how privileged mode and PMP are employed to build secure systems based on RISC-V architecture using FreeRTOS.
Currently, the mTower project supports:
Note that there may be variations in some hardware implementations of the H/W cores, as different manufacturers have their own architectural visions.
Future plans
In the future, we plan to focus on the following areas:
Contribution is Welcome
We welcome contributions to the mTower project, which is open-source. If you are a systems developer or an information security engineer, feel free to join our team and contribute to our research. Your participation would be greatly appreciated! You can find more information and get involved at the following link: https://github.com/Samsung/mTower
References
[1] https://www.mordorintelligence.com/industry-reports/risc-v-tech-market
[2] https://runtimerec.com/wp-content/uploads/2024/06/The-Rise-of-RISC-V-Microcontrollers.pdf
[3] https://octopart.com/pulse/p/10-top-trends-microcontrollers-2024
[4] https://riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf
[5] https://riscv.org/wp-content/uploads/2018/05/riscv-privileged-BCN.v7-2.pdf
[6] https://github.com/Samsung/mTower
[7] https://github.com/sifive
[8] https://www.sparkfun.com/products/retired/15594
[9] https://wiki.pine64.org/index.php?title=Ox64
[10] https://www.freertos.org/
